This invention relates generally to a semiconductor integrated circuit device having a semiconductor memory, and more particularly to a technique which can be effectively utilized for a static type RAM (random access memory) used in digital integrated circuits, for example.
Each memory cell in an MOS static RAM consists, for example, of a static type flip-flop circuit which in turn consists of a pair of driving MOSFETs whose gates and drains are cross-connected with one another and their load elements, and a pair of transfer gate MOSFETs. A memory array includes a plurality of these memory cells that are arranged in matrix, and a plurality of complementary data line pairs. The input/output terminals of memory cells are coupled to the complementary data lines corresponding thereof (see Japanese Patent Laid-Open No. 198594/1982).
It has been examined to build the static type RAM in a large scale digital integrated circuit used in compact or medium scale computers, and to let them operate in the same way as registers. In this case, since the RAM is used in the same manner as registers, their stored data must be often reset. Here, there occurs the problem that a relatively long period of time is necessary using the conventional method for resetting all the bits because the addresses of RAMs are sequentially selected and write of a reset signal (e.g. a logic "0") is effected for each such address. Therefore, it has been considered to provide a flip-flop circuit with an offset on the "0" side and to again turn on its power source after it is once cut off. In this case, the operation margin of the memory cell becomes small due to setting of the offset. Since the power source must be cut off before reset, other problems develop in that large noise occurs in a power line and the memory content of other RAMs can be destroyed when reset is carried out during the operation.